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riscv-rt: fix stack allocation for targets without M extension #364

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Merged
merged 1 commit into from
Nov 10, 2025
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riscv-rt: fix stack allocation for targets without M extension #364

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4 changes: 4 additions & 0 deletions riscv-rt/CHANGELOG.md
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Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
- Bump MSRV to 1.68 for latest syn 2.0 release
- Adapted to new `riscv` version.

### Fixed

- Fix stack allocation algorithm for multi-core targets without M extension

## [v0.16.0] - 2025-09-08

### Added
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10 changes: 5 additions & 5 deletions riscv-rt/src/asm.rs
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Expand Up @@ -105,13 +105,13 @@ _abs_start:
#[cfg(not(feature = "single-hart"))]
{
"mv t2, a0
lui t0, %hi(_hart_stack_size)
add t0, t0, %lo(_hart_stack_size)",
lui t1, %hi(_hart_stack_size)
add t1, t1, %lo(_hart_stack_size)",
#[cfg(riscvm)]
"mul t0, t2, t0",
"mul t0, t2, t1",
#[cfg(not(riscvm))]
"beqz t2, 2f // skip if hart ID is 0
mv t1, t0
"mv t0, x0
beqz t2, 2f // skip if hart ID is 0
1:
add t0, t0, t1
addi t2, t2, -1
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