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mimxrt/psram: Use lib functions in favor of direct register access.
Signed-off-by: Dryw Wade <dryw.wade@sparkfun.com>
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‎ports/mimxrt/psram.c‎

Lines changed: 140 additions & 120 deletions
Original file line numberDiff line numberDiff line change
@@ -30,49 +30,65 @@
3030
* THE SOFTWARE.
3131
*/
3232

33+
// This implementation is adapted from here:
34+
// https://github.com/PaulStoffregen/cores/blob/10025393e83ca9f4dc5646643a41cb2f32022ae4/teensy4/startup.c#L421-L615
3335
#include "py/mphal.h"
3436
#include "fsl_flexspi.h"
3537

3638
#if MICROPY_HW_ENABLE_PSRAM
3739

38-
// These #defines are from here:
39-
// https://github.com/PaulStoffregen/cores/blob/10025393e83ca9f4dc5646643a41cb2f32022ae4/teensy4/imxrt.h
40-
#define FLEXSPI_MCR2_CLRLEARNPHASE(x) ((uint32_t)(x << 14))
41-
#define FLEXSPI_LUTKEY_VALUE ((uint32_t)0x5AF05AF0)
40+
/*!
41+
* @brief Clock divider value.
42+
*
43+
* See https://www.pjrc.com/teensy/IMXRT1060RM_rev3_annotations.pdf (p1010 and p1050)
44+
*/
45+
typedef enum _clock_mux_value {
46+
kCLOCK_Flexspi2Mux_396MHz = 0U, /*!< FLEXSPI2 clock source is PLL2 PFD2. */
47+
kCLOCK_Flexspi2Mux_720MHz = 1U, /*!< FLEXSPI2 clock source is PLL3 PFD0. */
48+
kCLOCK_Flexspi2Mux_664_62MHz = 2U, /*!< FLEXSPI2 clock source is PLL3 PFD1. */
49+
kCLOCK_Flexspi2Mux_528MHz = 3U, /*!< FLEXSPI2 clock source is PLL2 (pll2_main_clk). */
50+
} clock_mux_value_t;
4251

43-
// The rest of the implementation is adapted from here:
44-
// https://github.com/PaulStoffregen/cores/blob/10025393e83ca9f4dc5646643a41cb2f32022ae4/teensy4/startup.c#L421-L615
45-
static void flexspi2_command(uint32_t index, uint32_t addr) {
46-
FLEXSPI2->IPCR0 = addr;
47-
FLEXSPI2->IPCR1 = FLEXSPI_IPCR1_ISEQID(index);
48-
FLEXSPI2->IPCMD = FLEXSPI_IPCMD_TRG(1);
49-
while (!(FLEXSPI2->INTR & FLEXSPI_INTR_IPCMDDONE(1))) {
50-
; // wait
51-
}
52-
FLEXSPI2->INTR = FLEXSPI_INTR_IPCMDDONE(1);
52+
static void flexspi2_command(uint32_t index, uint32_t addr, flexspi_port_t port) {
53+
flexspi_transfer_t xfer = {
54+
.deviceAddress = addr,
55+
.port = port,
56+
.cmdType = kFLEXSPI_Command,
57+
.seqIndex = index,
58+
.SeqNumber = 1,
59+
.data = NULL,
60+
.dataSize = 0,
61+
};
62+
FLEXSPI_TransferBlocking(FLEXSPI2, &xfer);
63+
FLEXSPI_ClearInterruptStatusFlags(FLEXSPI2, kFLEXSPI_IpCommandExecutionDoneFlag);
5364
}
5465

55-
static uint32_t flexspi2_psram_id(uint32_t addr) {
56-
FLEXSPI2->IPCR0 = addr;
57-
FLEXSPI2->IPCR1 = FLEXSPI_IPCR1_ISEQID(3) | FLEXSPI_IPCR1_IDATSZ(4);
58-
FLEXSPI2->IPCMD = FLEXSPI_IPCMD_TRG(1);
59-
while (!(FLEXSPI2->INTR & FLEXSPI_INTR_IPCMDDONE(1))) {
60-
; // wait
61-
}
62-
uint32_t id = FLEXSPI2->RFDR[0];
63-
FLEXSPI2->INTR = FLEXSPI_INTR_IPCMDDONE(1) | FLEXSPI_INTR_IPRXWA(1);
66+
static uint32_t flexspi2_psram_id(uint32_t addr, flexspi_port_t port) {
67+
uint32_t id = 0;
68+
flexspi_transfer_t xfer = {
69+
.deviceAddress = addr,
70+
.port = port,
71+
.cmdType = kFLEXSPI_Read,
72+
.seqIndex = 3,
73+
.SeqNumber = 1,
74+
.data = &id,
75+
.dataSize = 4,
76+
};
77+
FLEXSPI_TransferBlocking(FLEXSPI2, &xfer);
78+
FLEXSPI_ClearInterruptStatusFlags(FLEXSPI2,
79+
kFLEXSPI_IpCommandExecutionDoneFlag | kFLEXSPI_IpRxFifoWatermarkAvailableFlag);
6480
return id;
6581
}
6682

6783
/**
6884
* \return size of PSRAM in MBytes, or 0 if not present
6985
*/
70-
static uint8_t flexspi2_psram_size(uint32_t addr) {
86+
static uint8_t flexspi2_psram_size(uint32_t addr, flexspi_port_t port) {
7187
uint8_t result = 0; // assume we don't have PSRAM at this address
72-
flexspi2_command(0, addr); // exit quad mode
73-
flexspi2_command(1, addr); // reset enable
74-
flexspi2_command(2, addr); // reset (is this really necessary?)
75-
uint32_t id = flexspi2_psram_id(addr);
88+
flexspi2_command(0, addr, port); // exit quad mode
89+
flexspi2_command(1, addr, port); // reset enable
90+
flexspi2_command(2, addr, port); // reset (is this really necessary?)
91+
uint32_t id = flexspi2_psram_id(addr, port);
7692

7793
switch (id & 0xFFFF)
7894
{
@@ -127,116 +143,120 @@ size_t configure_external_ram() {
127143
IOMUXC->SELECT_INPUT_1[kIOMUXC_FLEXSPI2_IPP_IND_SCK_FA_SELECT_INPUT] = 1; // GPIO_EMC_25 for Mode: ALT8
128144

129145
// turn on clock (QSPI flash & PSRAM chips usually spec max clock 100 to 133 MHz)
130-
// CLOCK_SetDiv(kCLOCK_Flexspi2Div, 5); // 88.0 MHz
131-
// CLOCK_SetMux(kCLOCK_Flexspi2Mux, 3); // 88.0 MHz
132-
// CLOCK_SetDiv(kCLOCK_Flexspi2Div, 3); // 99.0 MHz
133-
// CLOCK_SetMux(kCLOCK_Flexspi2Mux, 0); // 99.0 MHz
134-
// CLOCK_SetDiv(kCLOCK_Flexspi2Div, 6); // 102.9 MHz
135-
// CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1); // 102.9 MHz
136-
CLOCK_SetDiv(kCLOCK_Flexspi2Div, 4); // 105.6 MHz
137-
CLOCK_SetMux(kCLOCK_Flexspi2Mux, 3); // 105.6 MHz
138-
// CLOCK_SetDiv(kCLOCK_Flexspi2Div, 5); // 110.8 MHz
139-
// CLOCK_SetMux(kCLOCK_Flexspi2Mux, 2); // 110.8 MHz
140-
// CLOCK_SetDiv(kCLOCK_Flexspi2Div, 5); // 120.0 MHz
141-
// CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1); // 120.0 MHz
142-
// CLOCK_SetDiv(kCLOCK_Flexspi2Div, 3); // 132.0 MHz
143-
// CLOCK_SetMux(kCLOCK_Flexspi2Mux, 3); // 132.0 MHz
144-
// CLOCK_SetDiv(kCLOCK_Flexspi2Div, 4); // 144.0 MHz
145-
// CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1); // 144.0 MHz
146-
// CLOCK_SetDiv(kCLOCK_Flexspi2Div, 3); // 166.2 MHz
147-
// CLOCK_SetMux(kCLOCK_Flexspi2Mux, 2); // 166.2 MHz
148-
// CLOCK_SetDiv(kCLOCK_Flexspi2Div, 2); // 176.0 MHz
149-
// CLOCK_SetMux(kCLOCK_Flexspi2Mux, 3); // 176.0 MHz
150-
CLOCK_EnableClock(kCLOCK_FlexSpi2);
151-
152-
FLEXSPI2->MCR0 |= FLEXSPI_MCR0_MDIS(1);
153-
FLEXSPI2->MCR0 = (FLEXSPI2->MCR0 & ~(FLEXSPI_MCR0_AHBGRANTWAIT_MASK
154-
| FLEXSPI_MCR0_IPGRANTWAIT_MASK | FLEXSPI_MCR0_SCKFREERUNEN(1)
155-
| FLEXSPI_MCR0_COMBINATIONEN(1) | FLEXSPI_MCR0_DOZEEN(1)
156-
| FLEXSPI_MCR0_HSEN(1) | FLEXSPI_MCR0_ATDFEN(1) | FLEXSPI_MCR0_ARDFEN(1)
157-
| FLEXSPI_MCR0_RXCLKSRC_MASK | FLEXSPI_MCR0_SWRESET(1)))
158-
| FLEXSPI_MCR0_AHBGRANTWAIT(0xFF) | FLEXSPI_MCR0_IPGRANTWAIT(0xFF)
159-
| FLEXSPI_MCR0_RXCLKSRC(1) | FLEXSPI_MCR0_MDIS(1);
160-
FLEXSPI2->MCR1 = FLEXSPI_MCR1_SEQWAIT(0xFFFF) | FLEXSPI_MCR1_AHBBUSWAIT(0xFFFF);
161-
FLEXSPI2->MCR2 = (FLEXSPI->MCR2 & ~(FLEXSPI_MCR2_RESUMEWAIT_MASK
162-
| FLEXSPI_MCR2_SCKBDIFFOPT(1) | FLEXSPI_MCR2_SAMEDEVICEEN(1)
163-
| FLEXSPI_MCR2_CLRLEARNPHASE(1) | FLEXSPI_MCR2_CLRAHBBUFOPT(1)))
164-
| FLEXSPI_MCR2_RESUMEWAIT(0x20) /*| FLEXSPI_MCR2_SAMEDEVICEEN*/;
165-
166-
FLEXSPI2->AHBCR = FLEXSPI2->AHBCR & ~(FLEXSPI_AHBCR_READADDROPT(1) | FLEXSPI_AHBCR_PREFETCHEN(1)
167-
| FLEXSPI_AHBCR_BUFFERABLEEN(1) | FLEXSPI_AHBCR_CACHABLEEN(1));
168-
uint32_t mask = (FLEXSPI_AHBRXBUFCR0_PREFETCHEN(1) | FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK
169-
| FLEXSPI_AHBRXBUFCR0_MSTRID_MASK | FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK);
170-
FLEXSPI2->AHBRXBUFCR0[0] = (FLEXSPI2->AHBRXBUFCR0[0] & ~mask)
171-
| FLEXSPI_AHBRXBUFCR0_PREFETCHEN(1) | FLEXSPI_AHBRXBUFCR0_BUFSZ(64);
172-
FLEXSPI2->AHBRXBUFCR0[1] = (FLEXSPI2->AHBRXBUFCR0[0] & ~mask)
173-
| FLEXSPI_AHBRXBUFCR0_PREFETCHEN(1) | FLEXSPI_AHBRXBUFCR0_BUFSZ(64);
174-
FLEXSPI2->AHBRXBUFCR0[2] = mask;
175-
FLEXSPI2->AHBRXBUFCR0[3] = mask;
176-
177-
// RX watermark = one 64 bit line
178-
FLEXSPI2->IPRXFCR = (FLEXSPI->IPRXFCR & 0xFFFFFFC0) | FLEXSPI_IPRXFCR_CLRIPRXF(1);
179-
// TX watermark = one 64 bit line
180-
FLEXSPI2->IPTXFCR = (FLEXSPI->IPTXFCR & 0xFFFFFFC0) | FLEXSPI_IPTXFCR_CLRIPTXF(1);
181-
182-
FLEXSPI2->INTEN = 0;
183-
FLEXSPI2->FLSHCR1[0] = FLEXSPI_FLSHCR1_CSINTERVAL(0)
184-
| FLEXSPI_FLSHCR1_TCSH(1) | FLEXSPI_FLSHCR1_TCSS(1);
185-
FLEXSPI2->FLSHCR2[0] = FLEXSPI_FLSHCR2_AWRSEQID(6) | FLEXSPI_FLSHCR2_AWRSEQNUM(0)
186-
| FLEXSPI_FLSHCR2_ARDSEQID(5) | FLEXSPI_FLSHCR2_ARDSEQNUM(0);
187-
188-
FLEXSPI2->FLSHCR1[1] = FLEXSPI_FLSHCR1_CSINTERVAL(0)
189-
| FLEXSPI_FLSHCR1_TCSH(1) | FLEXSPI_FLSHCR1_TCSS(1);
190-
FLEXSPI2->FLSHCR2[1] = FLEXSPI_FLSHCR2_AWRSEQID(6) | FLEXSPI_FLSHCR2_AWRSEQNUM(0)
191-
| FLEXSPI_FLSHCR2_ARDSEQID(5) | FLEXSPI_FLSHCR2_ARDSEQNUM(0);
192-
193-
FLEXSPI2->MCR0 &= ~FLEXSPI_MCR0_MDIS(1);
194-
195-
FLEXSPI2->LUTKEY = FLEXSPI_LUTKEY_VALUE;
196-
FLEXSPI2->LUTCR = FLEXSPI_LUTCR_UNLOCK(1);
197-
volatile uint32_t *luttable = &FLEXSPI2->LUT[0];
198-
for (int i = 0; i < 64; i++) { luttable[i] = 0;
199-
}
200-
FLEXSPI2->MCR0 |= FLEXSPI_MCR0_SWRESET(1);
201-
while (FLEXSPI2->MCR0 & FLEXSPI_MCR0_SWRESET(1)) {
202-
; // wait
146+
// CLOCK_SetDiv(kCLOCK_Flexspi2Div, kCLOCK_Flexspi2DivBy6); // 88.0 MHz
147+
// CLOCK_SetMux(kCLOCK_Flexspi2Mux, kCLOCK_Flexspi2Mux_528MHz); // 88.0 MHz
148+
// CLOCK_SetDiv(kCLOCK_Flexspi2Div, kCLOCK_Flexspi2DivBy4); // 99.0 MHz
149+
// CLOCK_SetMux(kCLOCK_Flexspi2Mux, kCLOCK_Flexspi2Mux_396MHz); // 99.0 MHz
150+
// CLOCK_SetDiv(kCLOCK_Flexspi2Div, kCLOCK_Flexspi2DivBy7); // 102.9 MHz
151+
// CLOCK_SetMux(kCLOCK_Flexspi2Mux, kCLOCK_Flexspi2Mux_720MHz); // 102.9 MHz
152+
CLOCK_SetDiv(kCLOCK_Flexspi2Div, kCLOCK_Flexspi2DivBy5); // 105.6 MHz
153+
CLOCK_SetMux(kCLOCK_Flexspi2Mux, kCLOCK_Flexspi2Mux_528MHz); // 105.6 MHz
154+
// CLOCK_SetDiv(kCLOCK_Flexspi2Div, kCLOCK_Flexspi2DivBy6); // 110.8 MHz
155+
// CLOCK_SetMux(kCLOCK_Flexspi2Mux, kCLOCK_Flexspi2Mux_664_62MHz); // 110.8 MHz
156+
// CLOCK_SetDiv(kCLOCK_Flexspi2Div, kCLOCK_Flexspi2DivBy6); // 120.0 MHz
157+
// CLOCK_SetMux(kCLOCK_Flexspi2Mux, kCLOCK_Flexspi2Mux_720MHz); // 120.0 MHz
158+
// CLOCK_SetDiv(kCLOCK_Flexspi2Div, kCLOCK_Flexspi2DivBy4); // 132.0 MHz
159+
// CLOCK_SetMux(kCLOCK_Flexspi2Mux, kCLOCK_Flexspi2Mux_528MHz); // 132.0 MHz
160+
// CLOCK_SetDiv(kCLOCK_Flexspi2Div, kCLOCK_Flexspi2DivBy5); // 144.0 MHz
161+
// CLOCK_SetMux(kCLOCK_Flexspi2Mux, kCLOCK_Flexspi2Mux_720MHz); // 144.0 MHz
162+
// CLOCK_SetDiv(kCLOCK_Flexspi2Div, kCLOCK_Flexspi2DivBy4); // 166.2 MHz
163+
// CLOCK_SetMux(kCLOCK_Flexspi2Mux, kCLOCK_Flexspi2Mux_664_62MHz); // 166.2 MHz
164+
// CLOCK_SetDiv(kCLOCK_Flexspi2Div, kCLOCK_Flexspi2DivBy3); // 176.0 MHz
165+
// CLOCK_SetMux(kCLOCK_Flexspi2Mux, kCLOCK_Flexspi2Mux_528MHz); // 176.0 MHz
203166

204-
}
205-
FLEXSPI2->LUTKEY = FLEXSPI_LUTKEY_VALUE;
206-
FLEXSPI2->LUTCR = FLEXSPI_LUTCR_UNLOCK(1);
167+
flexspi_config_t flexspi_config = {
168+
.rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackFromDqsPad,
169+
.enableSckFreeRunning = false,
170+
.enableCombination = false,
171+
.enableDoze = false,
172+
.enableHalfSpeedAccess = false,
173+
.enableSckBDiffOpt = false,
174+
.enableSameConfigForAll = false,
175+
.seqTimeoutCycle = 0xFFFF,
176+
.ipGrantTimeoutCycle = 0xFF,
177+
.txWatermark = 0,
178+
.rxWatermark = 0,
179+
.ahbConfig = {
180+
.enableAHBWriteIpTxFifo = false,
181+
.enableAHBWriteIpRxFifo = false,
182+
.ahbGrantTimeoutCycle = 0xFF,
183+
.ahbBusTimeoutCycle = 0xFFFF,
184+
.resumeWaitCycle = 0x20,
185+
.buffer = {
186+
{.priority = 0, .masterIndex = 0, .bufferSize = 512, .enablePrefetch = true},
187+
{.priority = 0, .masterIndex = 0, .bufferSize = 512, .enablePrefetch = true},
188+
{.priority = 0, .masterIndex = 0, .bufferSize = 0, .enablePrefetch = false},
189+
{.priority = 0, .masterIndex = 0, .bufferSize = 0, .enablePrefetch = false},
190+
},
191+
.enableClearAHBBufferOpt = false,
192+
.enableReadAddressOpt = false,
193+
.enableAHBPrefetch = false,
194+
.enableAHBBufferable = false,
195+
.enableAHBCachable = false,
196+
},
197+
};
198+
FLEXSPI_Init(FLEXSPI2, &flexspi_config);
199+
200+
FLEXSPI_DisableInterrupts(FLEXSPI2, kFLEXSPI_AllInterruptFlags);
201+
202+
flexspi_device_config_t flexspi_device_config = {
203+
.flexspiRootClk = 0,
204+
.isSck2Enabled = false,
205+
.flashSize = 1 << 16, // Default value, will be updated later
206+
.CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle,
207+
.CSInterval = 0,
208+
.CSHoldTime = 1,
209+
.CSSetupTime = 1,
210+
.dataValidTime = 0,
211+
.columnspace = 0,
212+
.enableWordAddress = false,
213+
.AWRSeqIndex = 6,
214+
.AWRSeqNumber = 1,
215+
.ARDSeqIndex = 5,
216+
.ARDSeqNumber = 1,
217+
.AHBWriteWaitUnit = kFLEXSPI_AhbWriteWaitUnit2AhbCycle,
218+
.AHBWriteWaitInterval = 0,
219+
.enableWriteMask = false,
220+
};
221+
FLEXSPI_SetFlashConfig(FLEXSPI2, &flexspi_device_config, kFLEXSPI_PortA1);
222+
FLEXSPI_SetFlashConfig(FLEXSPI2, &flexspi_device_config, kFLEXSPI_PortA2);
207223

224+
uint32_t cmd[64] = {0};
208225
// cmd index 0 = exit QPI mode
209-
FLEXSPI2->LUT[0] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_4PAD, 0xF5, 0, 0, 0);
226+
cmd[0] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_4PAD, 0xF5, 0, 0, 0);
210227
// cmd index 1 = reset enable
211-
FLEXSPI2->LUT[4] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x66, 0, 0, 0);
228+
cmd[4] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x66, 0, 0, 0);
212229
// cmd index 2 = reset
213-
FLEXSPI2->LUT[8] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x99, 0, 0, 0);
230+
cmd[8] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x99, 0, 0, 0);
214231
// cmd index 3 = read ID bytes
215-
FLEXSPI2->LUT[12] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x9F, kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_1PAD, 24);
216-
FLEXSPI2->LUT[13] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 1, 0, 0, 0);
232+
cmd[12] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x9F, kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_1PAD, 24);
233+
cmd[13] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 1, 0, 0, 0);
217234
// cmd index 4 = enter QPI mode
218-
FLEXSPI2->LUT[16] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x35, 0, 0, 0);
235+
cmd[16] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x35, 0, 0, 0);
219236
// cmd index 5 = read QPI
220-
FLEXSPI2->LUT[20] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_4PAD, 0xEB, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 24);
221-
FLEXSPI2->LUT[21] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 6, kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 1);
237+
cmd[20] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_4PAD, 0xEB, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 24);
238+
cmd[21] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 6, kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 1);
222239
// cmd index 6 = write QPI
223-
FLEXSPI2->LUT[24] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_4PAD, 0x38, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 24);
224-
FLEXSPI2->LUT[25] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD, 1, 0, 0, 0);
240+
cmd[24] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_4PAD, 0x38, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 24);
241+
cmd[25] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD, 1, 0, 0, 0);
242+
FLEXSPI_UpdateLUT(FLEXSPI2, 0, cmd, 64);
225243

226244
// Detected PSRAM size in MB
227245
uint8_t external_psram_size = 0;
228246

229247
// look for the first PSRAM chip
230-
uint8_t size1 = flexspi2_psram_size(0);
248+
uint8_t size1 = flexspi2_psram_size(0, kFLEXSPI_PortA1);
231249
if (size1 > 0) {
232-
FLEXSPI2->FLSHCR0[0] = size1 << 10;
233-
flexspi2_command(4, 0); // enter QPI mode
250+
flexspi_device_config.flashSize = size1 << 10;
251+
FLEXSPI_SetFlashConfig(FLEXSPI2, &flexspi_device_config, kFLEXSPI_PortA1);
252+
flexspi2_command(4, 0, kFLEXSPI_PortA1); // enter QPI mode
234253
// look for a second PSRAM chip
235-
uint8_t size2 = flexspi2_psram_size(size1 << 20);
254+
uint8_t size2 = flexspi2_psram_size(size1 << 20, kFLEXSPI_PortA2);
236255
external_psram_size = size1 + size2;
237256
if (size2 > 0) {
238-
FLEXSPI2->FLSHCR0[1] = size2 << 10;
239-
flexspi2_command(4, size1 << 20); // enter QPI mode
257+
flexspi_device_config.flashSize = size2 << 10;
258+
FLEXSPI_SetFlashConfig(FLEXSPI2, &flexspi_device_config, kFLEXSPI_PortA2);
259+
flexspi2_command(4, size1 << 20, kFLEXSPI_PortA2); // enter QPI mode
240260
}
241261
} else {
242262
// No PSRAM

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