@@ -9,14 +9,14 @@ use std::fmt;
99use std:: hash:: Hash ;
1010use std:: marker:: PhantomData ;
1111
12+ use binaryninja:: architecture:: ArchitectureExt ;
1213use binaryninja:: relocation:: { Relocation , RelocationHandlerExt } ;
1314use binaryninja:: {
1415 add_optional_plugin_dependency, architecture,
1516 architecture:: {
16- llvm_assemble, Architecture , ArchitectureExt , CoreArchitecture , CustomArchitectureHandle ,
17- ImplicitRegisterExtend , InstructionInfo , LlvmServicesCodeModel , LlvmServicesDialect ,
18- LlvmServicesRelocMode , Register as Reg , RegisterInfo , UnusedFlag , UnusedRegisterStack ,
19- UnusedRegisterStackInfo ,
17+ llvm_assemble, Architecture , CoreArchitecture , ImplicitRegisterExtend , InstructionInfo ,
18+ LlvmServicesCodeModel , LlvmServicesDialect , LlvmServicesRelocMode , Register as Reg ,
19+ RegisterInfo , UnusedFlag , UnusedRegisterStack , UnusedRegisterStackInfo ,
2020 } ,
2121 binaryview:: { BinaryView , BinaryViewExt } ,
2222 callingconvention:: { register_calling_convention, CallingConventionBase , ConventionBuilder } ,
@@ -624,14 +624,11 @@ impl<D: RiscVDisassembler> architecture::Intrinsic for RiscVIntrinsic<D> {
624624}
625625
626626struct RiscVArch < D : ' static + RiscVDisassembler + Send + Sync > {
627- handle : CoreArchitecture ,
628- custom_handle : CustomArchitectureHandle < RiscVArch < D > > ,
627+ handle : & ' static CoreArchitecture ,
629628 _dis : PhantomData < D > ,
630629}
631630
632631impl < D : ' static + RiscVDisassembler + Send + Sync > architecture:: Architecture for RiscVArch < D > {
633- type Handle = CustomArchitectureHandle < Self > ;
634-
635632 type RegisterInfo = Register < D > ;
636633 type Register = Register < D > ;
637634 type RegisterStackInfo = UnusedRegisterStackInfo < Self :: Register > ;
@@ -674,7 +671,7 @@ impl<D: 'static + RiscVDisassembler + Send + Sync> architecture::Architecture fo
674671 self . max_instr_len ( )
675672 }
676673
677- fn associated_arch_by_addr ( & self , _addr : & mut u64 ) -> CoreArchitecture {
674+ fn associated_arch_by_addr ( & self , _addr : & mut u64 ) -> & ' static CoreArchitecture {
678675 self . handle
679676 }
680677
@@ -977,29 +974,20 @@ impl<D: 'static + RiscVDisassembler + Send + Sync> architecture::Architecture fo
977974 Text ,
978975 ) ) ;
979976 } else {
980- res. push ( InstructionTextToken :: new (
981- "," ,
982- OperandSeparator ,
983- ) ) ;
977+ res. push ( InstructionTextToken :: new ( "," , OperandSeparator ) ) ;
984978 res. push ( InstructionTextToken :: new ( " " , Text ) ) ;
985979 }
986980
987981 match * oper {
988982 Operand :: R ( r) => {
989983 let reg = self :: Register :: from ( r) ;
990984
991- res. push ( InstructionTextToken :: new (
992- & reg. name ( ) ,
993- Register ,
994- ) ) ;
985+ res. push ( InstructionTextToken :: new ( & reg. name ( ) , Register ) ) ;
995986 }
996987 Operand :: F ( r) => {
997988 let reg = self :: Register :: from ( r) ;
998989
999- res. push ( InstructionTextToken :: new (
1000- & reg. name ( ) ,
1001- Register ,
1002- ) ) ;
990+ res. push ( InstructionTextToken :: new ( & reg. name ( ) , Register ) ) ;
1003991 }
1004992 Operand :: I ( i) => {
1005993 match op {
@@ -1032,10 +1020,7 @@ impl<D: 'static + RiscVDisassembler + Send + Sync> architecture::Architecture fo
10321020 Operand :: M ( i, b) => {
10331021 let reg = self :: Register :: from ( b) ;
10341022
1035- res. push ( InstructionTextToken :: new (
1036- "" ,
1037- BeginMemoryOperand ,
1038- ) ) ;
1023+ res. push ( InstructionTextToken :: new ( "" , BeginMemoryOperand ) ) ;
10391024 res. push ( InstructionTextToken :: new (
10401025 & if i < 0 {
10411026 format ! ( "-0x{:x}" , -i)
@@ -1046,15 +1031,9 @@ impl<D: 'static + RiscVDisassembler + Send + Sync> architecture::Architecture fo
10461031 ) ) ;
10471032
10481033 res. push ( InstructionTextToken :: new ( "(" , Brace ) ) ;
1049- res. push ( InstructionTextToken :: new (
1050- & reg. name ( ) ,
1051- Register ,
1052- ) ) ;
1034+ res. push ( InstructionTextToken :: new ( & reg. name ( ) , Register ) ) ;
10531035 res. push ( InstructionTextToken :: new ( ")" , Brace ) ) ;
1054- res. push ( InstructionTextToken :: new (
1055- "" ,
1056- EndMemoryOperand ,
1057- ) ) ;
1036+ res. push ( InstructionTextToken :: new ( "" , EndMemoryOperand ) ) ;
10581037 }
10591038 Operand :: RM ( r) => {
10601039 res. push ( InstructionTextToken :: new ( r. name ( ) , Register ) ) ;
@@ -2140,8 +2119,8 @@ impl<D: 'static + RiscVDisassembler + Send + Sync> architecture::Architecture fo
21402119 true
21412120 }
21422121
2143- fn handle ( & self ) -> CustomArchitectureHandle < Self > {
2144- self . custom_handle
2122+ fn core ( & self ) -> & ' static CoreArchitecture {
2123+ self . handle
21452124 }
21462125}
21472126
@@ -2869,22 +2848,18 @@ pub extern "C" fn CorePluginInit() -> bool {
28692848 binaryninja:: logger:: init ( log:: LevelFilter :: Trace ) . expect ( "Failed to set up logging" ) ;
28702849
28712850 use riscv_dis:: { RiscVIMACDisassembler , Rv32GRegs , Rv64GRegs } ;
2872- let arch32 =
2873- architecture:: register_architecture ( "rv32gc" , |custom_handle, core_arch| RiscVArch :: <
2874- RiscVIMACDisassembler < Rv32GRegs > ,
2875- > {
2876- handle : core_arch,
2877- custom_handle,
2878- _dis : PhantomData ,
2879- } ) ;
2880- let arch64 =
2881- architecture:: register_architecture ( "rv64gc" , |custom_handle, core_arch| RiscVArch :: <
2882- RiscVIMACDisassembler < Rv64GRegs > ,
2883- > {
2884- handle : core_arch,
2885- custom_handle,
2886- _dis : PhantomData ,
2887- } ) ;
2851+ let arch32 = architecture:: register_architecture ( "rv32gc" , |core_arch| RiscVArch :: <
2852+ RiscVIMACDisassembler < Rv32GRegs > ,
2853+ > {
2854+ handle : core_arch,
2855+ _dis : PhantomData ,
2856+ } ) ;
2857+ let arch64 = architecture:: register_architecture ( "rv64gc" , |core_arch| RiscVArch :: <
2858+ RiscVIMACDisassembler < Rv64GRegs > ,
2859+ > {
2860+ handle : core_arch,
2861+ _dis : PhantomData ,
2862+ } ) ;
28882863
28892864 arch32. register_relocation_handler ( "ELF" , |custom_handle, core_handler| {
28902865 RiscVELFRelocationHandler :: < RiscVIMACDisassembler < Rv32GRegs > > {
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